`include "common_def.v"
`include "decode_def.v"
module MODULE_EX_LS (
input         								clk_i,
input         								rst_i,
input													exe_valid_i,
input													lsu_ready_i,
output												ELSp_ready_o,
input													last_write_pr_en_i,
output												write_pr_en_o,
output												ls_start_o,
input													wash_i,//delete
input													fencei_end_i,

input   [`LOAD_NUM-1:0]      	load_data_key_i,
input   [7:0]					      	store_mask_i,
input     							    	read_en_i,
input         								write_en_i,
input   [`WIDTH-1:0] 		     	address_i,
input		[`WIDTH-1:0]					store_data_i,
input   							      	wenR_i,
input         								is_load_i,
input   [4:0] 					    	addr_dst_i,
input   [`WIDTH-1:0] 		     	data_dst_i,
input		[`WIDTH-1:0]					pc_i,//delete
input													add_nouse_inst_i,//delete
input													is_fencei_i,
input		[2:0]									ls_size_i,

output  [`LOAD_NUM-1:0]      	load_data_key_o,
output  [7:0]					      	store_mask_o,
output    							    	read_en_o,
output        								write_en_o,
output  [`WIDTH-1:0] 		     	address_o,
output	[`WIDTH-1:0]					store_data_o,
output  							      	wenR_o,
output        								is_load_o,
output  [4:0] 					    	addr_dst_o,
output  [`WIDTH-1:0] 		     	data_dst_o,
output	[`WIDTH-1:0]					pc_o,//delete
output												is_nouse_inst_o,//delete
output												is_fencei_o,
output		[2:0]									ls_size_o
);
//write_regs_en
wire write_regs_en;
wire exe_valid_r;
Reg #(1,0)exe_valid_reg(clk_i,rst_i,lsu_ready_i?0:exe_valid_i,exe_valid_r,exe_valid_i|lsu_ready_i);
wire write_regs_en = (exe_valid_r|exe_valid_i) & lsu_ready_i;
Reg #(1,0) ls_start_o_reg(clk_i,rst_i,write_regs_en,ls_start_o,1);
//ELSp_ready_o 
wire ELSp_ready;
wire ELSp_ready_r;
assign ELSp_ready = (exe_valid_r|exe_valid_i) & lsu_ready_i;
Reg #(1,1) ELSp_ready_o_reg(clk_i,rst_i, last_write_pr_en_i? 1'b0:ELSp_ready,ELSp_ready_r,ELSp_ready|last_write_pr_en_i);
assign ELSp_ready_o = ELSp_ready | ELSp_ready_r;
assign write_pr_en_o = write_regs_en;


Reg #(`LOAD_NUM,0)	reg_load_data_key_o(clk_i,rst_i,load_data_key_i,load_data_key_o,write_regs_en);
Reg #(8,0)	reg_store_mask_o(clk_i,rst_i,store_mask_i,store_mask_o,write_regs_en);
Reg #(1,0)	reg_read_en_o(clk_i,rst_i,read_en_i,read_en_o,write_regs_en);
Reg #(1,0)	reg_write_en_o(clk_i,rst_i,write_en_i,write_en_o,write_regs_en);
Reg #(`WIDTH,0)	reg_address_o(clk_i,rst_i,address_i,address_o,write_regs_en);
Reg #(`WIDTH,0)	reg_store_data_o(clk_i,rst_i,store_data_i,store_data_o,write_regs_en);
Reg #(1,0)	reg_wenR_o(clk_i,rst_i,wenR_i,wenR_o,write_regs_en);
Reg #(1,0)	reg_is_load_o(clk_i,rst_i,is_load_i,is_load_o,write_regs_en);
Reg #(5,0)	reg_addr_dst_o(clk_i,rst_i,addr_dst_i,addr_dst_o,write_regs_en);
Reg #(`WIDTH,0)	reg_data_dst_o(clk_i,rst_i,data_dst_i,data_dst_o,write_regs_en);
Reg #(`WIDTH,0)	reg_pc_o(clk_i,rst_i,pc_i,pc_o,write_regs_en);//delete
Reg #(1,0)	reg_is_nouse_inst_o(clk_i,rst_i,wash_i ?0:add_nouse_inst_i,is_nouse_inst_o,write_regs_en|wash_i);//delete
Reg #(1,0)	reg_is_fencei_o(clk_i,rst_i,fencei_end_i?0:is_fencei_i,is_fencei_o,write_regs_en|fencei_end_i);
Reg#(3,0) reg_ls_size_o(clk_i,rst_i,ls_size_i,ls_size_o,write_regs_en);
endmodule
